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197 SED1351 graphics lcd controller SED1351 n description the SED1351f is a graphics lcd controller capable of controlling medium to large resolution displays. it transfers data from mpu to external frame buffer ram and converts this data to display signals for lcd drivers. the SED1351f can display images with 4 gray shades and support display duty cycle as high as 1/ 1024. the SED1351f is designed to achieve high efficiency and data throughput to the lcd. it has a cycle steal mode which allows mpu to access frame buffer ram without interfering with the display operation. the SED1351f can directly interface with up to eight 64k-bit srams or two 256k-bit srams. the SED1351f can operate with either 5v or 3v power supply. the 5v version chip is the SED1351f0a and the 3v version chip is the SED1351flb. n features ? low-power cmos technology ? 8-bit or 16-bit mpu data interface ? direct interface with 80xx, z80 and 68xxx mpu ? 4- or 8-bit panel data bus for single panel and 4-bit bus for dual panel ? support logical or of layers and panel division ? smooth vertical scrolling ? virtual screen display up to 1024 ? binary mode (on/off only) generates black & white images ? gray mode (on/off and two gray steps) gener- ates images with 4 gray shades ? maximum number of rows binary mode ............ 2048 gray mode .............. 1024 ? maximum number of rows: single panel ............ 1024 dual panel ............... 2048 ? maximum display sizes when 64k-byte srams are used: binary mode ............ 2048 256 / 1024 512 gray mode .............. 1024 256 / 512 512 ? available models: SED1351f 0a ............ 5v, qfp5-100 pin SED1351f lb ............ 3v,qfp15-100 pin n system block diagram SED1351f sram 8 of 8k 8 or 2 of 32k 8 clock mono lcd mpu 80xx z80 68xxx data address control
198 SED1351 n interface with 8-bit mpu (z-80) and 64k-bit sram (8 of 8k x 8) a0~a12 i/o1~i/o8 cs(0) we a0~a12 i/o1~i/o8 cs(1) we a0~a12 i/o1~i/o8 cs(2) we a0~a12 i/o1~i/o8 cs(3) we a0~a12 i/o1~i/o8 cs(4) we a0~a12 i/o1~i/o8 cs(5) we a0~a12 i/o1~i/o8 cs(6) we a0~a12 i/o1~i/o8 cs(7) we 8k 8 decoder mmu decoder ud0~ud3,ld0~ld3 yd lp xscl fr a0~a15 iocs mpusel memcs db0~db7 iord iowr memrd memwr ready reset mpulck mono lcd a0~a15 memrq ioreq d0~d7 rd wr wait reset clk z80 SED1351f va0~va12 vd0~vd7 vcs0~vcs7 vwe note: example implementation, actual may vary.
199 SED1351 n interface with 16-bit mpu (8086) and 64k-bit sram (8 of 8k x 8) ud0~ud3,ld0~ld3 yd lp xscl fr a0~a12 i/o1~i/o8 cs(0) we a0~a12 i/o1~i/o8 cs(2) we a0~a12 i/o1~i/o8 cs(4) we a0~a12 i/o1~i/o8 cs(6) we a0~a12 i/o1~i/o8 cs(1) we a0~a12 i/o1~i/o8 cs(3) we a0~a12 i/o1~i/o8 cs(5) we a0~a12 i/o1~i/o8 cs(7) we 8k 8 mono lcd va0~va12 vd0~vd7 vcs0 we mpuclk memrd memwr iord iowr mpusel memcs bhe ab0~ab15 iocs db0~db15 reset ready clk ready reset clk ready reset rdy vcs2 vcs4 vcs6 vd8~vd15 vcs1 vcs3 vcs5 vcs7 decoder +5v decoder d0~d15 m/io bhe a16~a19 a0~a15 t oe stb oe clk s2 s1 s0 den dt/r ale s2 s1 s0 bhe a16~a19 ad0~ad15 mrdc amwc iorc aiowc 8286 8282 8086 (maximum mode) 8284a 8288 SED1351 min/max note: example implementation, actual may vary.
200 SED1351 n interface with 16-bit mpu (68000) and 256k-bit sram (2 of 32k x 8) a0~a14 i/o1~i/o8 cs(1) we a0~a14 i/o1~i/o8 cs(0) we va1~va15 vd0~vd7 vcs0 vwe vd8~vd15 vcs1 ud0~ud3,ld0~ld3 yd lp xscl fr 32k 8 32k 8 mono lcd dack ready iocs memcs iord iowr ab0 bhe ck fc0,1,2 a[16?3] a[1?5] as r/w lds uds 68000 memrd ab1?b15 decoder qd memwr note: example implementation, actual may vary.
201 SED1351 display maximum display size sram cpu sram ram monochrome 4 grayscale type interface interface xyxy 8k 256 256 256 128 1 of 8k 8 8 bit 8 bit 16k 512 256 256 256 2 of 8k 8 8 bit 8 bit 16 bit 16 bit 24k 512 384 384 256 3 of 8k 8 8 bit 8 bit 32k 512 512 512 256 4 of 8k 8 8 bit 8 bit 16 bit 16 bit 1 of 32k 8 8 bit 8 bit 48k 768 512 512 384 6 of 8k 8 8 bit 8 bit 16 bit 16 bit 56k 896 512 512 448 7 of 8k 8 8 bit 8 bit 64k 1024 512 512 512 8 of 8k 8 8 bit 8 bit 16 bit 16 bit 2 of 32k 8 8 bit 8 bit 16 bit 16 bit n supported resolutions n block diagram i/o control address buffer data buffer basic training generation oscillator mpx refresh address counter vram control display data control mpx 16 bits display timing control control register r1 to r15 iocs,lowr, iord memcs, memwr, memrd ab0 ~ ab15 bhe db0 ~ db15 lcdenb xscl lp yd wf ud0 ~ ud3 ld0 ~ ld3 vd0 ~ vd15 vwe va0 ~ va15 vcs0 ~ vcs4 osc2 osc1 ready reset mpusel, mpuclk
202 SED1351 n electrical characteristics ? SED1351f0a ? absolute maximum ratings parameter symbol ratings unit supply voltage v dd v ss C0.3 to 7.0 v input voltage v i v ss C0.3 to v dd +0.3 v output voltage v o v ss C0.3 to v dd +0.3 v output current/pin i o 10 ma power dissipation p d 200 mw supply current i dd /i ss 40 ma storage temperature t stg C65 to 150 c soldering temperature and time t sol 260 c, 10s (at lead) (v ss = 0v) ? recommended operating conditions parameter symbol condition min typ max unit supply voltage v dd 4.5 5.0 5.5 v input voltage v i v ss v dd v operating temperature t opr C20 75 c (v ss = 0v)
203 SED1351 dc characteristics (f0a) parameter symbol condition min typ max unit static current i dds v in = v dd , v dd = max, 100 m a v ss , i oh = i ol = 0 v dd = 5.5v, input leakage current (type 1) i li v ih = v dd , C10 10 m a v il = v ss high level input voltage 1 (osc1) v ih1 v dd = 5.5v 3.5 v low level input voltage 1 (osc1) v il1 v dd = 4.5v 1.0 v high level input voltage 2 (type 2) v ih2 v dd = 5.5v 2.0 v low level input voltage 2 (type 2) v il2 v dd = 4.5v 0.8 v high level input voltage 3 (type 3) v t+ v dd = 5.5v 4.0 v low level input voltage 3 (type 3) v tC v dd = 4.5v 0.8 v hysteresis voltage (type 3) v h v dd = 5v 0.3 v high level output voltage 1 (type 4) v oh1 v dd = 4.5v v dd v i oh = C2ma C 0.4 low level output voltage 1 (type 4) v ol1 i ol = 6ma v ss v + 0.4 high level output voltage 2 (osc2) v oh2 v dd = 4.5v v dd v i oh = C50 m a C 0.4 low level output voltage 2 (osc2) v ol2 i ol = 50 m a v ss v + 0.4 (ta = C20 to 75 c) note: type 1. memcs, memwr, memrd, iocs, iowr, iord, mpuclk, ab0 ~ ab15, bhe, mpusel, reset, osc type 2. memcs, memwr, memrd, iocs, iowr, iord, mpuclk, ab0 ~ ab15, bhe, db0 ~ db15, vd0 ~ vd15 type 3. mpusel, reset type 4. db0 ~ db15, ready, va0 ~ va15, vcs0 ~ vcs4, vd0 ~ vd15, vwe, xscl, lp, wf, yd, ud0 ~ ud3, ld0 ~ ld3, lcdenb
204 SED1351 ? SED1351fla ? absolute maximum ratings parameter symbol ratings unit supply voltage v dd v ss C0.3 to 7.0 v input voltage v i v ss C0.3 to v dd +0.5 v output voltage v o v ss C0.3 to v dd +0.5 v output current/pin i o 24 ma power dissipation p d 200 mw supply current i dd /i ss 40 ma storage temperature t stg C65 to 150 c (v ss = 0v) ? recommended operating conditions parameter symbol condition min typ max unit supply voltage v dd 2.7 3.6 v input voltage v i v ss v dd v operating temperature t opr C20 75 c (v ss = 0v)
205 SED1351 dc characteristics (flb) parameter symbol condition min typ max unit static current i dds v in = v dd or v ss ,30 m a v dd = max, i oh = i ol = 0 v dd = max, input leakage current (type 1) i l v ih = v dd ,C11 m a v il = v ss high level input voltage 1 (osc1) v ih1 v dd = max 0.7v dd v low level input voltage 1 (osc1) v il1 v dd = min 0.2v dd v high level input voltage 2 (type 2) v ih2 v dd = max 0.7v dd v low level input voltage 2 (type 2) v il2 v dd = min 0.2v dd v high level input voltage 3 (type 3) v t+ v dd = max 0.8v dd v low level input voltage 3 (type 3) v tC v dd = min 0.2v dd v hysteresis voltage (type 3) v h v dd = typ 0.3 v high level output voltage 1 (type 4) v oh1 v dd = min v dd v i oh = C1.5ma C 0.3 low level output voltage 1 (type 4) v ol1 i ol = 3ma v ss v + 0.3 high level output voltage 2 (osc2) v oh2 v dd = min v dd v i oh = C50 m a C 0.4 low level output voltage 2 (osc2) v ol2 i ol = 50 m a v ss v + 0.4 (ta = C20 to 75 c) note: type 1. memcs, memwr, memrd, iocs, iowr, iord, mpuclk, ab0 ~ ab15, bhe, mpusel, reset, osc type 2. memcs, memwr, memrd, iocs, iowr, iord, mpuclk, ab0 ~ ab15, bhe, db0 ~ db15, vd0 ~ vd15 type 3. mpusel, reset type 4. db0 ~ db15, ready, va0 ~ va15, vcs0 ~ vcs4, vd0 ~ vd15, vwe, xscl, lp, wf, yd, ud0 ~ ud3, ld0 ~ ld3, lcdenb
206 SED1351 n pin configuration (f0a) va3 va2 va1 va0 vwe db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 1 80 100 vd11 vd12 vd13 vd14 vd15 lcdenb xscl lp wf yd ud0 ud1 ud2 ud3 ld0 ld1 ld2 ld3 osc1 osc2 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 v ss v dd iocs iowr iord memcs memwr memrd ready mpuclk reset mpusel bhe ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 db0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 v ss v dd vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vcs0 vcs1 vcs2 vcs3 vcs4 va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 va5 va4 50 81 31 30 51 SED1351f oa n pin configuration (flb) vd8 vd9 vd10 vd11 vd12 vd13 vd14 vd15 lcdenb xscl lp wf yd ud0 ud1 ud2 ud3 ld0 ld1 ld2 ld3 osc1 osc2 v ss v dd v ss va4 va3 va2 va1 va0 vwe db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 ab15 ab14 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 iocs iowr iord memcs memwr memrd ready mpuclk reset mpusel bhe ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vcs0 vcs1 vcs2 vcs3 vcs4 va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 va5 v dd 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 76 100 51 75 25 1 50 26 SED1351f lb
207 SED1351 pin name type f0a flb drv description pin no. pin no. db0 to db15 i/o 30 to 45 28 to 43 these pins are interfaced with the mpu data bus. when using an 8-bit mpu, connect db8 to db15 to vdd. ab0 to ab15 i 14 to 29 12 to 27 these pins are interfaced with the mpu address bus. if multiplexed address signals are used, connect them via latch circuits. a control register is selected by ab0 to ab3. correspondence of the mpu address bus to the vram address bus is such that abi = vai (where i is a pin number). bhe i 13 11 this signal is a bus high enable signal where a 16-bit mpu is used. it goes l (low) when an odd address is encountered. when using an 8-bit mpu configuration, connect the bhe pin to vdd. iocs i 3 1 this pin selects a control register contained in the SED1351. it is l active, and must be assigned to mpu i/o space. iowr i 4 2 this signal is used for writing data into a control register contained in the SED1351. it is l active, and must go l when it encounters an out instruction from the mpu. iord i 5 3 this signal is used for reading data from a control register contained in the SED1351. it is l active, and must go l when it encounters an in instruction from the mpu. memcs i 6 4 this signal is used for selecting vram. it is l active, and must be assigned to mpu memory space. memwr i 7 5 this signal is used for writing data to the vram. it is l active, and must go l when it encounters a memory write instruction from the mpu. memrd i 8 6 this signal is used for reading data from the vram. it is l active, and must go l when it encounters a memory read instruction from the mpu. ready o 9 7 this signal requests the mpu to wait. it goes l by the falling edge of iocs or memcs. it goes h by the rising edge of mpuclk after completion of the SED1351 internal processing. since ready is not a tri-state pin, it needed not be pulled up and must be connected directly to the ready (wait) terminal of the mpu. mpuclk i 10 8 this pin accepts an mpu clock. the mpu wait state is cleared by the rising edge of mpuclk. mpusel i 12 10 this signal is connected to either vdd or vss for selection of an mpu. mpusel = v ss 8-bit mpu (e.g., z80, v20, i8088) mpusel = v dd 16-bit mpu (e.g., v30, i8086) reset i 11 9 the mpu reset signal comes to this pin. it is h active, and initializes a control register. n pin description 1. system connector terminals (at mpu)
208 SED1351 combinations of control pins iocs iowr iord memcs memwr memrd operation 1 * * 1 * * invalid 001111 write to control register 010111 read from control register 111001 write to vram 111010 read from vram note: any combination other than those listed above will cause a system error. 1 = h (high) 0 = l (low) * = dont care 2. vram connector terminals pin name type f0a flb drv description pin no. pin no. vd0 to vd15 i/o 68 to 78, 68 to 83 these pins are interfaced with the vram data bus. 81 to 85 for a 16-bit mpu configuration, vd0 to vd7 must be connected to even addresses, and vd8 to vd15 to odd addresses. for an 8-bit configuration, vd8 to vd15 must be connected to vdd. va0 to va12 o 47 to 59 45 to 49, these pins are interfaced with the vram address 52 to 59 bus and chip select pins. va13/vcs7 to o 60 to 62 60 to 62 the SED1351 has chip select pins that can directly va15/vcs5 control eight 64k srams (8k bytes each) or two vcs0 to vcs4 o 67 to 63 67 to 63 256k srams (32k bytes) in the 64k vram space. see technical manual for details. vwe o 46 44 this signal is used for writing data to the vram. it is l active, and must be connected to the we pin of the vram. 3. oscillator terminals pin name type f0a flb drv description pin no. pin no. osc1 i 99 97 the osc1 (input) and osc2 (output) pins gener- osc2 o 100 98 ate clocks for internal operation. they allow crystal oscillation and external clock input. 4. power terminals pin name type f0a flb drv description pin no. pin no. v dd 2, 79 51, 100 the power supply pins include two v dd s and two v ss 1, 80 50, 99 v ss s. apply +5v or +3v to v dd and 0v to v ss . a capacitor (4.7 m f or more) must be connected near each pair of v dd /v ss pins.
209 SED1351 5. lcd connector terminals pin name type f0a flb drv description pin no. pin no. ud0 to ud3 i/o 91 to 94 89 to 92 lcd display data. ud0 to ud3 are the upper panel ld0/ud4 to o 95 to 98 93 to 96 display data in the signal panel or double panel ld3/ud7 drive panel mode. ld0/ud4 to ld3/ud7 are the lower panel display data in the double panel drive mode. ud0 to ud3, and ld0/ud4 to ld3/ud7 are used for 8- bit data transfer in the single panel drive mode. xscl o 87 85 this single is a shift clock for display data transfer. take the ud0 to ud3, ld0/ud4 to ld3/ud7 display data into lcds by the falling edge of xscl. lp o 88 86 this pin provides both a display data latch pulse and a scan signal transfer clock. upon completion of trans- ferring the lcd data on one line, display data can be latched or a scan signal transferred by the falling edge of lp. wf o 89 87 this pin provides a frame signal used for lcd ac driving. yd o 90 88 this pin provides a scanning line start pulse. the signal is h active. allow the scanning line drive ic to take in yd by the falling edge of lp. the SED1351 has two lines of retracing; if two scan- ning line drive ics are cascade-connected for the upper and lower panels in the double panel drive mode, two lines must be provided between the upper and lower scanning line drive outputs. lcdenb o 86 84 this pin provides the data which is set in bit 1 (d1) of the mode register (r1). lcdenb goes l when the system is reset; it can be effectively used for lcd power control.
210 SED1351 illustrated below are the display data which are output from the ud0 to ud3, ld0/ud4 to ld3/ud7 and the display on the panel: ud3 ud2 ud1 ud0 . . . . . . . . . . . . dual panel ?top ld3 ld2 ld1 ld0 dual panel ?bottom ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 8-bit single panel ud3 ud2 ud1 ud0 ud3 ud2 ud1 ud0 4-bit single panel n lcd panel pixels 640 dots (top view) lower lcd panel upper lcd panel 240 lines 240 lines 1 - 1 2 - 1 1 - 2 2 - 2 1 - 639 2 - 639 1 - 640 2 - 640 240 - 1 241 - 1 240 - 2 241 - 2 240- 639 241- 639 240- 640 241- 640 480 - 1 480 - 2 480- 639 480- 640
211 SED1351 n monochrome lcd panel interface 8-bit dual monochrome panel (i.e. 640 480) lp : 242 pulses xscl: 160 clocks line 240/480 line 1/241 line 2/242 line 4/244 line 3/243 line 2/242 line 1/241 yd lp wf ud[3:0], ld[3:0] lp wf xscl ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 line 239/479 1? 1? 1?37 1? 1? 1?38 1? 1? 1?39 1? 1? 1?40 241? 241? 241?37 241? 241? 241?38 241? 241? 241?39 241? 241? 241?40
212 SED1351 n monochrome lcd panel interface 4-bit single monochrome panel (i.e. 320 480) lp : 482 pulses xscl: 80 clocks line 480 line 1 line 2 line 4 line 3 line 2 line 1 yd lp wf ud[3:0] lp wf xscl ud3 ud2 ud1 ud0 line 479 1? 1? 1?17 1? 1? 1?18 1? 1? 1?19 1? 1? 1?20 8-bit single monochrome panel (i.e. 640 480) lp : 482 pulses xscl: 80 clocks line 480 line 1 line 2 line 4 line 3 line 2 line 1 yd lp wf ud[3:0], ld[3:0] lp wf xscl ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 line 479 1? 1? 1?33 1? 1?0 1?34 1? 1?1 1?35 1? 1?2 1?36 1? 1?3 1?37 1? 1?4 1?38 1? 1?5 1?39 1? 1?6 1?40
213 SED1351 n package dimensions ? SED1351f0a qfp5-100pin unit: mm actual size 19.6 0.4 index 81 100 50 31 130 80 51 25.6 0.4 20 0.1 0.65 0.1 0.30 0.1 14 0.1 1.5 0.3 0.15 0.05 2.7 0.1 0 ~12 2.8 ? SED1351flb actual size qfp15-100pin unit: mm 14.0 0.1 index 76 100 50 26 125 75 51 0 ~ 12 1.0 1.4 0.1 0.5 0.2 0.5 0.1 16.0 0.4 14.0 0.1 0.125 0.05 0.18 0.1 16.0 0.4
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